1. Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a semiconductor memory which is free from the influence of a noise produced in the detection of read-out information.
2. Description of the Prior Art
A semiconductor memory has an arrangement such, for example, as shown in FIG. 1 for detecting read-out information of the stored content of a selected memory cell. In FIG. 1, reference character MCA indicates a memory cell array in which a plurality of memory cells, each formed by a bipolar transistor, are arranged; SA designates a sense amplifier; and R1, R2 and Q.sub.1, Q.sub.2 respectively identify resistors and transistors which make up a detector circuit. Bias currents I.sub.1 and I.sub.2 are always applied to the transistors Q.sub.1 and Q.sub.2 for their high-speed operation and, in accordance with the store state of a selected memory cell, either one of read currents Is.sub.1 and Is.sub.2 for the memory cell array MCA is zero and the other assumes a certain value. Depending on this, voltage drops across the resistors R1 and R2 differ in magnitude and the difference voltage is amplified by the sense amplifier SA to produce a read output OUT. Reference character V.sub.R denotes a reference voltage which is applied to the bases of the transistors Q.sub.1 and Q.sub.2 ; and Vcc represents a power source voltage.
If the currents Is.sub.1 and Is.sub.2 are switched ideally, then the read output OUT becomes a correspondingly ideal one. In a transient state of the operation of a switching circuit accompanying a memory access, however, cases are sometimes met with, where Is.sub.1 =Is.sub.2 =0 or Is.sub.1, Is.sub.2 =0 to make the waveform of the read output OUT indistinct, resulting in a read error.
Assuming that the currents Is.sub.1 and Is.sub.2 vary each time an address ADDR is established, as shown in FIG. 2, the output OUT' from the sense amplifier SA may sometimes assume a level intermediate between levels "1" and "0" corresponding to the characteristic of the detector circuit as shown. That is, the output does not immediately reverse from the level "1" to "0" but assumes the intermediate level once and then reverses. Furthermore, when the relationship between the currents Is.sub.1 and Is.sub.2 are changed by a switching noise or the like, the output OUT corresponding thereto is obtained; namely, the output is affected by the noise. With increased capacity of the memory cell, the load on a word line increases and a hold current decreases. As a result of this, the rise and fall of the word line potential are delayed and the both detected currents concurrently flow to the same amplifier SA for a certain period of time, as described above; in this case, the intermediate level is introduced into the amplified output from the sense amplifier SA. This phenomenon is prominent when an address includes a skew. With a view to overcoming such a defect, there has been proposed such a circuit arrangement as shown in FIG. 3 in which the sense amplifier SA is a latch type one.
In FIG. 3, reference character Ish indicates a hold current. In this example, the sense amplifier SA operates only when the difference between the read currents Is.sub.1 and Is.sub.2 becomes larger than the hold current Ish; namely, the sense amplifier SA has a hysteresis characteristic. In other words, even if the waveforms of the read currents Is.sub.1 and Is.sub.2 are unstable, the waveforms do not directly appear in the sense amplifier SA because of the latch operation, and consequently the output waveform is improved. In this circuit arrangement, however, the hold current Ish flows at all times and the sense amplifier SA does not start its operation unless the difference between the read currents Is.sub.1 and Is.sub.2 exceeds the hold current Ish; namely, the circuit operation is delayed by the rise time until the above difference exceeds the hold current, resulting in the defect that the read rate is sacrificed.